1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs). The present invention relates to, for example, an electro-optical device represented by a liquid crystal display device and a structure of electrical equipment (electronic apparatus) on which an electro-optical device is mounted as a part. Also, the present invention relates to a method of manufacturing the device. Note that the semiconductor device in this specification indicates a device in general, which can function by utilizing a semiconductor characteristic, and the electro-optical device and the electrical equipment (electronic apparatus) each fall under the category of the semiconductor device.
2. Description of the Related Art
A technique for performing a thermal anneal method, a laser anneal method, or both of a thermal anneal method and a laser anneal method for crystallizing an amorphous semiconductor film formed on an insulating substrate made of glass or the like to form a crystalline semiconductor film or improving crystallinity thereof is widely studied. A silicon film is often used as the above semiconductor film. Note that a crystalline semiconductor film in this specification indicates a semiconductor film having a crystalline structure.
A crystalline semiconductor film has significantly higher mobility than an amorphous semiconductor film. Thus, when the crystalline semiconductor film is used, for example, an active matrix liquid crystal display device (semiconductor device in which thin film transistors (TFTs) for a pixel portion and a driver portion are formed on a single substrate) which cannot be realized by a semiconductor device produced using a conventional amorphous semiconductor film can be manufactured.
However, when an amorphous semiconductor film formed by a plasma CVD method or a sputtering method is subjected to a thermal anneal method or a laser anneal method to form a crystalline semiconductor film, a crystal orientation thereof becomes out of control because of its arrangement in an arbitrary direction in many cases. Thus, when a TFT is manufactured using the crystalline semiconductor film, this becomes a factor for limiting an electrical characteristic thereof.
There is an EBSP (electron backscatter diffraction pattern) method as a method of analyzing a crystal orientation of the surface of the crystalline semiconductor film. The EBSP is a method of analyzing a crystal orientation of the surface of the crystalline semiconductor film. According to this method, crystal orientations in which crystal grains at respective measurement points are directed to the surface can be indicated in different colors. Alternatively, a certain measurement point is to be noted and a region located within a deviation angle of a crystal orientation set by a measurer (allowable deviation angle) can be separately indicated in an adjacent point. The allowable deviation angle can be freely set by a measurer. In this specification the allowable deviation angle is set to be 15°, and when a certain point is to be noted, a region that a deviation angle of a crystal orientation in an adjacent point is 15° or smaller is called a grain. The reason why the allowable deviation angle is set to be 15° is that a general set value is 15°. The grain is composed of a plurality of crystal grains. However, since an allowable deviation angle of a crystal orientation in the grain is small, it can be microscopically assumed to be a single crystal grain.
Also, there is a method described in Japanese Patent Application Laid-open No. Hei 7-183540 as one of the methods of crystallizing, an amorphous semiconductor film. Here, the method will be briefly described. First, a metallic element such as nickel, palladium, or lead in a very small amount is added to an amorphous semiconductor film. A plasma processing method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like is preferably used as the adding method. After the addition, the amorphous semiconductor film is exposed to, for example, a nitrogen atmosphere at 550° C. for 4 hours to form a crystalline semiconductor film. When a TFT is made from such a crystalline semiconductor film, not only the improvement of field effect mobility but also a reduction in a subthreshold coefficient (S value) are produced. Thus, an electrical characteristic can be dramatically improved. A heating temperature, a heating time, and the like, which are most suitable for crystallization, depend on the amount of metallic elements to be added and a state of the amorphous semiconductor film. Also, when this crystallization method is used, it is confirmed that an alignment of a crystal orientation can be improved to be a single direction.
FIG. 16A shows a grain in a semiconductor film formed using the above crystallization method. Concretely, an amorphous silicon film having a film thickness of 65 nm is formed on a synthetic quartz glass substrate by an LPCVD apparatus. After that, a nickel acetate aqueous solution (weight converting concentration: 5 ppm, volume: 10 ml) is applied onto the surface of the amorphous silicon film by spin coating to thereby form a metal containing layer, and thermal treatment (at 600° C. for 12 hours) is performed for crystallizing the semiconductor film. Then, in order to observe a crystal orientation of a grain and a boundary thereof by an optical microscope, the semiconductor film is immersed in 0.5% hydrofluoric acid for 30 seconds to thereby remove an oxide film and further immersed in a KOH/IPA solution for 30 seconds. After such anisotropic etching, a grain observed by an optical microscope (bright field reflection mode, 200 times) is shown in FIG. 16A. FIG. 16B is a schematic view of FIG. 16A.
Incidentally, it is known that there is an internal stress in a thin film formed by a known film formation technique such as a CVD method (chemical vapor deposition method) or a sputtering method. The internal stress includes an intrinsic stress and a thermal stress caused by a difference in thermal expansion coefficients between a thin film and a substrate.
With respect to the thermal stress, its influence can be neglected by considering a material of a substrate and a process temperature. However, a mechanism for generating the intrinsic stress is not necessarily clarified, and it is considered that the intrinsic stress is generated by complicated relations among, a growth process of a film and changes in a phase and in a composition due to later thermal treatment and the like.
Generally, the internal stress includes a tensile stress and a compression stress. As shown in FIG. 17A, when a thin film 401 is to be contracted against a substrate 402, since the substrate 402 pulls the thin film in such a direction that the contraction is hindered, they are deformed such that the thin film is located inside the substrate. This is called a tensile stress. On the other hand, as shown in FIG. 17B, when the thin film 401 is to be extended, since the substrate 402 is contracted, they are formed such that the thin film 401 is located outside the substrate. This is called a compression stress. Generally, in many cases, a tensile stress is indicated by a symbol “+” and a compression stress is indicated by a symbol “−”.
In the case where TFTs are made from a crystalline semiconductor film, when the crystalline semiconductor film is divided for element isolation by patterning, variations are caused in active regions, in particular, channel forming regions, of respective TFTs. That is, there are an active region in which a large number of grain boundaries exist in a grain, an active region which is composed of only substantially a single grain, and the like. Also, when a semiconductor film is crystallized using a metallic element for promoting crystallization, a crystal grain produced using the metallic element as a nucleus and a crystal grain produced by generating a natural nucleus (in this specification, a nucleus in the case where a nucleus of the produced crystal grain is not a metallic element is defined as the natural nucleus) are mixed. Thus, a variation in a physical property of the semiconductor film is caused. Note that, when a temperature becomes high such as 600° C. or higher or a time required for crystallization becomes long, it is known that the natural nucleus is easy to generate. Such a variation becomes a cause of a variation in an electrical characteristic and a cause of uneven display in the case where the TFT is used for a display portion of various kinds of semiconductor devices.
Therefore, a method of suppressing a variation in the number of grains in active regions, in particular, channel forming regions, of the respective TFTs by reducing a size of a grain is considered. In order to reduce a size of a grain, a generation density of a crystal nucleus may be increased. In other words, surface energy of the semiconductor film is decreased or a chemical potential of the semiconductor film is increased to reduce a radius of a critical nucleus and increase a generation density of a crystal nucleus. As one method of realizing this, there is a method of adding a large amount of metallic elements for promoting crystallization to the semiconductor film to change surface energy and a chemical potential of the semiconductor film. When this method is used, since a large number of crystal nuclei due to the metallic element are generated, a size of a grain can be reduced. However, in the case of the above method, there is a problem that excessive amounts of metallic elements are left as metallic compounds in high resistance regions (channel forming region and offset region). Since the metallic compounds are easy to flow a current, resistances of regions formed as the high resistance regions are reduced and this becomes a cause of deteriorating, stability and reliability in an electrical characteristic of a TFT.